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HD49815TF digital camera signal processor ade-207-316 (z) 1st edition sep. 1999 description the HD49815TF is a cmos ic that has been developed as a digital signal-processing ic for ccd-camera digital-signal-processing systems. functions ccd-sensor drive-pulse generation (tg) digital agc (automatic gain control) color signal separation circuit rgb matrix rgb gain rgb and y gamma color-difference matrix enhancer rgb and y setup digital i/f (4:2:2) zoom control mirror reversal synchronization signal generator for encoding (ssg) awb, ae, and af detection two-channel 8-bit d/a converter features the HD49815TF provides camera-signal processing, tg, ssg, zoom, and d/a functions and other functions in a single chip and supports high system-integration level. in conjunction with the hd49323af-01 (cds/agc + 10-bit adc) and the control microcomputer, the HD49815TF forms a three-chip kit that can implement an optimal ccd-camera digital-signal- processing system. the HD49815TF provides the zoom function and controls the 1- to 256- times linear zoom. it also provides the half-mirror function.
HD49815TF 2 features (cont) since the HD49815TF can be made compatible with the former product, hd49811tfa, through software, a shorter development term is enabled. since software controls awb, ae, and af, any protocol can be prepared according to the camera shooting conditions. programmable tg enables use of any ccd device. system block diagram HD49815TF ccd hd49323af-01 lens c-signal output y-signal output r-y/b-y digital output y-signal digital output color processing zoom processing luminance processing input line memory micro- processor i/f tg ssg system control ae (iris) control awb (white balance) control v.driver 8-bit single-chip microcomputer (h8 series) encode dac cds/agc+ 10-bit adc
HD49815TF 3 pin arrangement 31 (top view) tfp-120 xsub dkf_ld t_cp(test) ty_k sdi sdck sld sdo ep(1) ep(2) bf hd_in m_ck v dd v ss fv hd cblk csync scblk hsync id idp v dd v ss x1i x1o ids mck_s reset zoom_hd fp nme cpi(1) cpi(2) cpi(3) cpi(4) cpi(5) cpi(6) cpi(7) cpi(8) cpo(1) cpo(2) cpo(3) cpo(4) v ss v dd cpo(5) cpo(6) cpo(7) cpo(8) ypi(1) ypi(2) ypi(3) ypi(4) ypi(5) ypi(6) ypi(7) ypi(8) ypo(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pll_n pll_p vr x2i x2o fsc v ss av dd v ss av dd v ss c_out cbu cbl rext y_out v ss av dd v ss v dd v ss dick nryby ypo(8) ypo(7) ypo(6) ypo(5) ypo(4) ypo(3) ypo(2) xsg2 xsg1 xv4 xv3 xv2 xv1 v dd rg v dd h2 h1 v dd obp sp2 sp1 v ss v dd dsp_mck cpref adck ad(1) ad(2) ad(3) ad(4) ad(5) ad(6) ad(7) ad(8) ad(9) ad(10) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
HD49815TF 4 pin description pin no. symbol pin name i/o description i/o format 1 xsub ccd shutter pulse o ccd control pulse zc2r 2 dkf_ld line input ld i line input dedicated load ics 3 t_cp test i test pin (gnd input) ic 4 ty_k title sw i title-killer sw (1 = on, 0 = off) icd 5 sdi state data input i state data-setting data input ic 6 sdck state data clock i state data-setting clock ics 7 sld state data load pulse i state data-latch pulse ics 8 sdo awb, ae, data output o awb, ae, and af detection-data output zc2r 9 ep (1) ae window pulse 1 o iris detection-area-setting pulse: sp-a7 [8] output changeover iczc2r 10 ep (2) ae window pulse 2 o iris detection-area-setting pulse: sp-a7 [8] output changeover iczc2r 11 bf burst flag o burst flag output iczc2r 12 hd_in external csync input i external csync input icsd 13 m_ck microprocessor clock o microprocessor clock output (1/2 or 1/4 dividing of x?al 1) oc2r 14 v dd v cc 2 3.3 v power supply vcci 15 v ss gnd gnd gndi 16 fv field vertical output o vertical synchronization pulse iczc2r 17 hd hd output o horizontal synchronization pulse iczc2r 18 cblk blanking pulse o blanking pulse iczc2r 19 csync sync output o sync pulse iczc2r 20 scblk sc blanking pulse o subcarrier blanking pulse (secam) iczc2r 21 hsync horizontal sync o horizontal sync pulse (secam) oc2r 22 id identity o secam determination pulse oc2r 23 idp identity pulse o secam determination pulse iczc2r 24 v dd v cc 2 3.3 v power supply vccc 25 v ss gnd gnd gndc 26 x1i x?al 1 input i 2fsc oscillator input iq3 27 x1o x?al 1 output o 2fsc oscillator output oq3 28 ids line id reset input i line-determination-signal input icd 29 mck_s mck output sw i pin 13 mck dividing setting sw (1 = 1/2, 0 = 1/4) ic 30 reset reset i reset: to restore the initial data settings ics
HD49815TF 5 pin description (cont) pin no. symbol pin name i/o description i/o format 31 pll_n pll negative o pll signal output zc2 32 pll_p pll positive o pll signal output zc2 33 vr vertical reset i vertical synchronization signal input icsd 34 x2i x?al 2 input i 4fsc oscillator input iq2 35 x2o x?al 2 output o 4fsc oscillator output oq2 36 fsc sub carrier frequency o fsc output iczc2r 37 v ss gnd gnd gnda 38 av dd analog v cc 2 analog system power supply: 3.3 v vcca 39 v ss gnd gnd gnda 40 av dd analog v cc 2 analog system power supply: 3.3 v vcca 41 v ss gnd gnd gnda 42 c_out c analog signal output o chrominance-signal analog output oa 43 cbu current buffer upper i d/a upper current source ia 44 cbl current buffer lower i d/a lower current source ia 45 rext reference resister ext i reference voltage input ia 46 y_out y analog signal output o luminance-signal analog output oa 47 v ss gnd gnd gnda 48 av dd analog v cc 2 analog system power supply: 3.3 v vcca 49 v ss gnd gnd gnda 50 v dd v cc 2 digital system power supply: 3.3 v vcci 51 v ss gnd gnd gndi 52 dick digital interface clock o digital interface clock output iczc2r 53 nryby r-y, b-y phase output o color-difference signal phase clock iczc2r 54 ypo (8) y parallel output (8); msb o luminance-signal digital output msb oc2r 55 ypo (7) y parallel output (7) o luminance-signal digital output oc2r 56 ypo (6) y parallel output (6) o luminance-signal digital output oc2r 57 ypo (5) y parallel output (5) o luminance-signal digital output oc2r 58 ypo (4) y parallel output (4) o luminance-signal digital output oc2r 59 ypo (3) y parallel output (3) o luminance-signal digital output oc2r 60 ypo (2) y parallel output (2) o luminance-signal digital output oc2r 61 ypo (1) y parallel output (1) ; lsb o luminance-signal digital output lsb oc2r 62 ypi (8) y parallel input (8); msb i luminance-signal digital input msb icd 63 ypi (7) y parallel input (7) i luminance-signal digital input icd 64 ypi (6) y parallel input (6) i luminance-signal digital input icd
HD49815TF 6 pin description (cont) pin no. symbol pin name i/o description i/o format 65 ypi (5) y parallel input (5) i luminance-signal digital input icd 66 ypi (4) y parallel input (4) i luminance-signal digital input icd 67 ypi (3) y parallel input (3) i luminance-signal digital input icd 68 ypi (2) y parallel input (2) i luminance-signal digital input icd 69 ypi (1) y parallel input (1); lsb i luminance-signal digital input lsb icd 70 cpo (8) c parallel output (8); msb o chrominance-signal digital output msb oc2r 71 cpo (7) c parallel output (7) o chrominance-signal digital output oc2r 72 cpo (6) c parallel output (6) o chrominance-signal digital output oc2r 73 cpo (5) c parallel output (5) o chrominance-signal digital output oc2r 74 v dd v cc 2 3.3 v power supply vcco 75 v ss gnd gnd gndo 76 cpo (4) c parallel output (4) o chrominance-signal digital output oc2r 77 cpo (3) c parallel output (3) o chrominance-signal digital output oc2r 78 cpo (2) c parallel output (2) o chrominance-signal digital output oc2r 79 cpo (1) c parallel output (1); lsb o chrominance-signal digital output lsb oc2r 80 cpi (8) c parallel input (8); msb i chrominance-signal digital input msb icd 81 cpi (7) c parallel input (7) i chrominance-signal digital input icd 82 cpi (6) c parallel input (6) i chrominance-signal digital input icd 83 cpi (5) c parallel input (5) i chrominance-signal digital input icd 84 cpi (4) c parallel input (4) i chrominance-signal digital input icd 85 cpi (3) c parallel input (3) i chrominance-signal digital input icd 86 cpi (2) c parallel input (2) i chrominance-signal digital input icd 87 cpi (1) c parallel input (1); lsb i chrominance-signal digital input lsb icd 88 nme memory hd output o line memory control output iczc2dr 89 fp field pulse o field pulse iczc2r 90 zoom_hd zoom hd output o horizontal synchronization signal iczc2r 91 ad (10) ad input (10); msb i a/d data input msb ic 92 ad (9) ad input (9) i a/d data input ic 93 ad (8) ad input (8) i a/d data input ic 94 ad (7) ad input (7) i a/d data input ic
HD49815TF 7 pin description (cont) pin no. symbol pin name i/o description i/o format 95 ad (6) ad input (6) i a/d data input ic 96 ad (5) ad input (5) i a/d data input ic 97 ad (4) ad input (4) i a/d data input ic 98 ad (3) ad input (3) i a/d data input ic 99 ad (2) ad input (2) i a/d data input ic 100 ad (1) ad input (1); lsb i a/d data input lsb ic 101 adck ad clock o a/d converter clock iczc2r 102 cpref clamp reference output o clamp reference pulse 2c3 103 dsp_mck microprocessor clock output o microprocessor clock output: sp-a7 [8] output changeover iczc2r 104 v dd v cc 2 3.3 v power supply vcco 105 v ss gnd gnd gndo 106 sp1 sampling pulse 1 o sampling pulse for the agc/cds ic iczc2 107 sp2 sampling pulse 2 o sampling pulse for the agc/cds ic iczc2 108 obp obp pulse o optical black-pulse output iczc2r 109 v dd v cc 1 3 v or 5 v power supply (h1/h2 power supply) vccc35 110 h1 h1 o ccd-sensor horizontal drive pulse oc3r 111 h2 h2 o ccd-sensor horizontal drive pulse oc3r 112 v dd v cc 1 5 v power supply (rg power supply) vccc5 113 rg reset gate o ccd-sensor control reset gate zc3r 114 v dd v cc 2 3.3 v power supply vcco 115 xv1 xv1 o ccd-sensor vertical control pulse iczc2r 116 xv2 xv2 o ccd-sensor vertical control pulse iczc2r 117 xv3 xv3 o ccd-sensor vertical control pulse iczc2r 118 xv4 xv4 o ccd-sensor vertical control pulse iczc2r 119 xsg1 xsg1 o ccd-sensor vertical control pulse zc2r 120 xsg2 xsg2 o ccd-sensor vertical control pulse zc2r
HD49815TF 8 description of i/o format i/o format contents ic cmos level input icd cmos level input with pull-down resistor ics cmos level schmitt input icsd cmos level input with pull-down resistor iczc2 cmos level common i/o (4 ma) iczc2dr cmos level common i/o with pull-down resistor and through-put control (4 ma) iczc2r cmos level common i/o with through-put control (4 ma) oc2r cmos level output with through-put control (4 ma) oc3r cmos level output with through-put control (8 ma) iq2 crystal oscillator input oq2 crystal oscillator output iq3 crystal oscillator input oq3 crystal oscillator output zc2 cmos-level three-state output (4 ma) zc2r cmos-level three-state output with through-put control (4 ma) zc3 cmos-level three-state output (8 ma) zc3r cmos-level three-state output with through-put control (8 ma) vcci core system power supply: 3 v vcco puddling system power supply: 3 v vccc common power supply: 3 v vccc5 common power supply: 5 v for pin 112 vccc35 common power supply: 3 or 5 v for pin 109 gndi core system gnd gndo puddling system gnd gndc common gnd ia analog input oa analog output vcca analog power supply gnda analog gnd notes: 1. pin 113 is used for 5 v system output. 2. pins 110 and 111 are used for 3 v or 5 v system output. they depend on the voltage of pin 109.
HD49815TF 9 block diagram 16 16 16 16 16 16 agc 10-bit a/d input 16 dsp_mck 16 to vdriver ccd 16 to cds/agc fv, chd etc. 16 m_ck x'tal 2 x'tal 1 dl 1hdl 1hdl sw y setup digital interface rgb setup lpf lpf de-knee memory control wb detec- tion wb + + + + + line sw h.v enhancer 7.5ire + c- limit pre- filter rgb matrix yl matrix c-g titler mod c.dac y.dac rgb gain 8-bit c y y out c out 8-bit af detection axis conver- sion clk conver- sion luminance correction fade sw sw sw sw sw sw blk zoom function 16 16 16 16 microprocessor interface 16 16 16 16 16 16 timing generator ssg fv, hd, mck, mcks pllp, plln, fsc, cblk cp, csync, ep1-3 idp, scblk, etc. adck, obp, sp1 sp2, pblk h1, h2, rg, xv1 to 4 xsg1,2, xsub base clipp- ing ae detection axis conver- sion (wb) gamma correc- tion gamma correc- tion highlight enhancer sdo sld sdck sdi cpi ypi cpo ypo
HD49815TF 10 absolute maximum ratings (ta = 25 c) item symbol ratings unit power supply voltage v cc ?.2 to +6.8 v pin voltage (5 v operation block) vt5v ?.2 to v cc 1 +0.2 v pin voltage (3 v operation block) vt3v ?.2 to v cc 2 +0.2 v output current per output io ?2 to +32 ma per gnd-v cc pair iot ?2 to +72 ma allowable power dissipation popr 450 mw operating temperature topr ?0 to +75 c storage temperature with bias tbias ?0 to +75 c without bias tstg ?0 to +125 c notes: 1. using this lsi at values in excess of the absolute maximum ratings may permanently damage the lsi. the lsi should normally be operated under the conditions specified for the electrical characteristics. exceeding these conditions may lead to incorrect operation and may adversely affect lsi reliability. 2. all voltage values are referenced to gnd = 0 v. 3. the pin voltage ratings also apply to the nc pins. 4. v cc 1 indicates the 5 v system power supply and v cc 2 indicates the 3 v system power supply.
HD49815TF 11 electrical characteristics (v cc 1 = 4.75 v to 5.25 v, v cc 2 = 2.85 v to 3.15 v, av cc = 2.85 v to 3.15 v, ta = 25 c) item symbol min typ max unit test conditions note cmos-level v ihc v cc 2 0.75 v cc 2v input voltage v ilc 0.0 v cc 2 0.20 v cmos schmitt v tc + 2.50 v cc 2vv cc 1 = 5 v input voltage v tc 0.0 0.60 v v cc 2 = 3 v output voltage v ohc1 v cc 1?.5 v i o h = ?00 m a 5 v system pin 1 v olc1 0.4 v i o l = 200 m a 5 v system pin v ohc2 v cc 2?.5 v i o h = ?00 m a 3 v system pin 1, 5 v olc2 0.4 v i o l = 200 m a 3 v system pin 1, 6 input leakage current i li 1.0 m av in = 0 v to v cc 2 output leakage current i lo 1.0 m a output hi-z conditions 2 pull-down current i pd 5 100 m av in = v cc 2 = 3 v power dissipation popr 450 mw v cc 1 = 5 v, v cc 2 = 3 v, av cc = 3 v 3 analog output voltage (full scale) vfull 0.80 1.00 1.20 v 3, 4 analog output voltage (zero scale) vzero ?.20 0.00 0.20 v differential linearity dnl ?.0 2.0 lsb notes: 1. output voltage must be measured in the steady state. 2. except for pins that include a pull-down resistor. 3. guaranteed at cbu = 0.1 m f, cbl = 0.1 m f, rext = 3.4 k w , analog output load resistance = 500 w , and ta = 25 c. 4. applied to pins indicated as oa in the i/o format column of the pin-functions table. 5. because v oh of pin 31 cannot be measured logically, it was not tested. 6. because v ol of pin 32 cannot be measured logically, it was not tested. 7. v cc 1, v cc 2, and av cc indicate the 5 v system power supply, the 3 v system power supply, and the analog system power supply, respectively. v cc indicates v cc 1, v cc 2, and av cc . 8. the voltage range of pin 109 (vccc35) is v cc = 2.85 v to 5.25 v.
HD49815TF 12 crystal oscillation circuit 1. measuring conditions the oscillation frequency was measured under the following conditions. v cc 1 = 5.0 v v cc 2 = 3 v ta = 25 c 8 mhz, 20 mhz, and 24 mhz: rf = 1 to 10 m w cin, cout = 20 pf ( 20 pf) 32 mhz: rf = 1 to 10 m w cin = 20 pf ( 20 pf) cout = 100 pf ( 20 pf), co = 15 pf ( 5 pf), lout = 1 m h the conditions above may be changed within the range of measuring conditions. 2. measuring method under the measuring conditions above, two methods were tested. fmin. = 20 mhz, and fmax. = 32 mhz (applied to pins 26 and 27) fmin. = 8 mhz, and fmax. = 24 mhz (applied to pins 34 and 35) note: the oscillation start time tosc is max. = 200 ms. 3. measuring circuit xout cout cin co lout note: the part enclosed by the dotted line in the above circuit is used when measuring at 32 mhz. to the internal circuit monitor pin xin dividing counter counter figure 1 measuring circuit
HD49815TF 13 built-in functions and system configuration system configuration HD49815TF ccd hd49323af-01 lens xv1 to 4 initial setting resistor input and ae, awb detection data output sp1/2 h1, h2 agc gain setting tg ssg v.driver cds/agc+ 10-bit adc c-signal output y-signal output r-y/b-y digital output y-signal digital output color processing zoom processing luminance processing input line memory micro- processor i/f system control ae (iris) control awb (white balance) control 8-bit single-chip microcomputer (h8 series) encode dac figure 2 system configuration system description 1. ccd the following lists the pixels of the ccd sensors that can be used with the HD49815TF. for other pixel numbers, contact our sales dept. 512 (h) 492 (v) ntsc 512 (h) 582 (v) pal 682 (h) 492 (v) ntsc 681 (h) 582 (v) pal 2. cds/agc + 10-bit adc the hd49323af-01 (manufactured by hitachi) is recommended as an optimal cds/agc + 10-bit adc ic for the HD49815TF. since the hd49323af-01 provides a correlated double sampling circuit that realizes high s/n and an automatic gain control (agc) circuit that implements programmable control of 0 db to 34.7 db, it enables a high-image-quality camera system when used in conjunction with the HD49815TF.
HD49815TF 14 3. 8-bit single-chip microcomputer the 8-bit single-chip microcomputer controls the system. it receives the image detection data that the HD49815TF is gathering and implements automatic iris control (ae), automatic white balance control (awb), and automatic focus control (af). when setting the power on, this microcomputer implements the initial setting to the state data of the HD49815TF. for details on the state data, see ?itachi camera dsp (HD49815TF) state data? built-in functions 1. input line memory block 16 16 agc to the color-signal processing block 10-bit a/d input dl 1hdl 1hdl to the luminance-signal processing block de-knee memory control + figure 3 input line memory block a. de-knee function when the cds/agc ic at the pre-stage or the external circuit uses the knee circuit to expand the dynamic range of the signal, the de-knee (inverse knee) circuit returns the signal converted by the knee circuit to the original state. the de-knee point can be set in state data sp_a0 [1]. the gain of the high-luminance block is 1/2. b. agc function a digital agc circuit is provided. the agc gain can be set in state data sp_a0 [2] from 1 to 16 times. c. 1h delay line (1hdl) function this circuit obtains horizontal efficient pixels of the ccd output signal. the number of efficient pixels is set in state data sp_a0 [9, 10] and tm_a0 [14] mcset.
HD49815TF 15 2. color-signal processing block rgb setup to the awb detection block to the luminance signal processing block wb + + line sw c- limit pre- filter rgb matrix gamma correc- tion yl matrix base clipp- ing c-g rgb gain axis conver- sion axis conver- sion (wb) from the input line memory block to the zoom function figure 4 color-signal processing block a. c-limit (complementary color clipping level) function high clipping processing is performed on the complementary color signals independently. high clipping is set in state data sp_a2 [0 to 3]. the complementary color signal indicates gb: (g + cy), wr: (ye + mg), wb: (mg + cy), and gr: (g + ye). b. rgb-matrix block the three primary colors (red, green, and blue) are acquired in the rgb matrix by multiplying arbitrary coefficients by the four complementary colors (gb, wr, wb, and gr) and taking the total of those results. the rgb matrix is designed to support the minimum color moire and to enable free color reproduction. arbitrary coefficients are set in state data sp_a2 [4 to 15]. the following shows the formula. gb wr wb gr kra kba kga state data sp_a2 [4 to 15] = r b g krb kbb kgb krc kbc kgc krd kbd kgd c. rgb-setup block the black level of the color signals is variable according to the coefficients of the rgb matrix. the value calculated by the formula below is subtracted from the color signal to correct the black level. the subtracted value can be set externally and is set in state data sp_a3 [0 to 2]. formula = - [48 s (matrix data) 2 3 ] d. rgb-gain block the rgb gain value acquired in the awb control is set in the rgb gain circuit to improve the white reproduction performance. as it is set prior to the gamma correction, it changes the gamma correction amount. the rgb gain can be set in state data sp_a3 [3 to 5] from 1 to 256 times. (the g gain is set from 1 to 128 times.)
HD49815TF 16 e. c gamma ( g ) correction block the c gamma correction circuit performs gamma processing on the rgb signal. it is set in state data sp_a3 [6 to 9]. four kinds of values can be set independently, according to the input-signal level, to acquire optimal gamma characteristics: the c gamma dark (to reduce the gain of the small signals for improving s/n), c gamma coefficient (to control the expansion of the gamma curve), c gamma knee (to decide the slope of the large signals), and c gamma limit (to perform high-clipping processing for the input signal of the c gamma circuit). f. yl matrix block the luminance level changes according to the color temperature of the imaged object. set state data sp_a5 [12, 13] for the luminance correction. to correct the luminance, create yl from the three primary colors (r, g, and b) and convert it to the luminance signal level. the yl matrix circuit creates the yl level from the rgb signal. the yl matrix is set in state data sp_a3 [11 to 13]. g. the axis-conversion (c-y matrix) block the c-y (color-difference) matrix takes r-g and b-g as its input signals, and creates the r-y and b-y color-difference signals by setting coefficients for those inputs. the axis-conversion (c-y matrix) circuits are set in state data sp_a8 [0 to 5]. h. base-clipping block since base clipping is performed on the color-difference signals, the base-clipping circuit has the characteristics of clipping the sections near axes on a vector scope. this circuit is set in state data sp_a8 [8]. 3. luminance-signal-processing block y setup to the awb- detection block from yl matrix + h.v enhancer highlight enhancer 7.5ire + gamma correc- tion luminance correction fade from the input line memory block to the zoom function figure 5 luminance-signal-processing block a. h-enhancer function the h-enhancer circuit allows the core level, the enhancer gain, and the noise coefficient to be set independently to acquire optimal characteristics. this circuit is set in state data sp_a4 [4 to 7]. b. v-enhancer function the v-enhancer circuit allows the enhancer coefficient to be set and can control the gain for only those signal components that exceed the set core level. this circuit is set in state data sp_a4 [8 to 10].
HD49815TF 17 c. luminance correction the ratio of the red and blue levels changes according to the color temperature of the imaged object. for example, if a red object is imaged at a low color temperature, the luminance level increases and the object appears to have a lower chrominance. therefore, the luminance correction circuit performs luminance-correction processing to implement color depth reproduction. the luminance-correction circuit is set in state data sp_a5 [12, 13]. d. y setup since the ob clamp processes the signal, the black level of the 10-bit signal input to the HD49815TF is fixed to 48/1024. the y-setup circuit subtracts 48 at the black level. however, when 48 at the black level differs due to the noise mixed in the analog signal, the y-setup circuit subtracts that value. the y-setup circuit is set in state data sp_a5 [6]. e. gamma correction the gamma-correction circuit implements the gamma-correction processing for the separated y signal. four kinds of values can be set independently, according to the input-signal level, to acquire optimal gamma characteristics: the gamma input limit, the gamma knee coefficient, the gamma coefficient, and the gamma black clipping. the gamma correction circuit is set in state data sp_a5 [1 to 4]. f. highlight enhancer for input-y signal levels in excess of 100 ire, the highlight enhancer implements highlight enhancer processing. this circuit is set in state data sp_a5 [0, 5, and 14]. g. fade the fade circuit amplifies the luminance signal by a factor of 0 to 1. this circuit is set in state data sp_a5 [9]. 4. zoom, encode block, tg, ssg, and awb and ae detection blocks a. zoom processing the y, r-y, and b-y signals completed the color-signal processing and the luminance-signal processing can be electronically zoomed by a factor of 1 to 256. after clipping ccd signals for v direction, zoom circuit clips these signals for h direction, and expand these signals for h and v directions. the zooming times and the read starting position for the v and h directions are set in state data tm_a2 [3, 4, 5, 6, 8, and 9] and zm_a0 to 6. b. encode block this circuit encodes the signals completed the color-signal processing, the luminance-signal processing, and the zoom processing as the ntsc/pal tv-monitor method. a dac that converts the digital signal to an analog signal is provided. the dac has two channels: one for r-y signals and one for b-y signals.
HD49815TF 18 c. tg and ssg the tg generates the signals required to drive the ccd sensor (h1, h2, rg, sg1/2, and the v transfer pulse), and the cds/agc control signals (sp1 and sp2). in addition, the ssg generates the signals to synchronize with the tv monitor (the sync signal). the drive timing of the generated signals differs according to the manufacturer and the specifications of the ccd sensor. setting the state data enables setting of any timing. the state data of tg and ssg can be set in tm_a0, a1, a2, a3, and a8. d. awb- and ae-detection blocks the HD49815TF provides automatic white-balance (awb) and automatic-iris (ae) detection circuits that are indispensable for a camera. the awb-detection block takes the r-y and b-y color-difference signals completed the color- signal processing, and converts to the r-b and mg-g axes. the converted signals are sent to circuits for the white detection to obtain white signal components only, and the white-color difference value is detected. the 8-bit single-chip microcomputer acquires this detection data, and controls the r and b gains to produce the true white. the state data of the awb detection is awb_a0 and a8. the ae-detection block divides the ccd output signal converted to digital by the 10-bit adc to six arbitrary areas, and performs integration processing. this function enables detection of the lighting level of the image signal. the 8-bit single-chip microcomputer acquires this detection data, and controls the accumulation amount (the shutter) of the ccd sensor or the iris motor of the lens to maintain the proper lighting. the state data of the af detection is ae_a0 to a7 and a8.
HD49815TF 19 microcomputer interface specifications sld (pin 7) d1 lsb msb sdck (pin 6) sdi (pin 5) write format read format notes: synchronous serial transfer (the microcomputer serial port can be used.) transfer frequency: 3.58 mhz or lower data and address are handled in a byte unit. the clock and load pulse are used in common for read/write. 1. 2. 3. 4. sdo (pin 8) d2 d3 d4 d5 d6 d7 d8 d1 msb d2 d3 d4 d5 d6 d7 d8 d1 lsb lsb msb d2 d3 d4 d5 d6 d7 d8 1 byte data (n byte) data (n byte) std3-----sth2-----std1 address stal stah stal stah sdi (pin 5) d1 msb d2 d3 d4 d5 d6 d7 d8 d1 lsb lsb msb d2 d3 d4 d5 d6 d7 d8 msb 1 byte or 2 byte sld (pin 7) sdck (pin 6) lsb hi-z hi-z function address (write address) function address
HD49815TF 20 data transfer specification for data transfer between the HD49815TF and the microcomputer, two types (n and e for write, and r1 and r2 for read) are available. the following table shows the relationship between the function block and the transfer specifications. on the next page, the details of the transfer specifications are described. function block transfer mode transfer specifications * 1 related address signal processing w n sp_a0, 2 to 5, 7 to 10, 15 tm w n tm_a3, 15 e tm_a0 to 2, 8, 10 to 12 r r1 tmr_a0 iris w n ae_a0 to 7 r r2 ae_a8 white balance w n awb_a0 r r1 awb_a8 af w n af_a0 to 3 r r1 af_a8 to 13 zoom w n zm_a0 to 6 note: 1. transfer specifications type n : normal transfer from the microcomputer to the dsp type e : transfer using the set pulse (synchronous with vd) or the reset signal (used as a synchronous pulse in the dsp) sent from the microcomputer to the rs latch in the dsp note: this cannot be set during the standby mode. type r1 : data transfer (1) from the dsp to microcomputer type r2 : data transfer (2) from the dsp to microcomputer
HD49815TF 21 type n sld (pin 7) transfer specification pulse timing conditions a = 100 ns or more b = 100 ns or more c = 100 ns or more sdck (pin 6) abc n type e sld (pin 7) sdck (pin 6) b d a e 100 ns 650 ns or more 300 ns or more 150 ns or more 70 ns 485 ns or more 240 ns or more 135 ns or more fs d b a 270,000 pixels 410,000 pixels 0.5 / fs + 100 ns or more 2 / fs + 100 ns or more 5.5 / fs + 100 ns or more sensor clock transfer specification pulse timing conditions type r1 sld (pin 7) sdck (pin 6) ab d r1 a = 100 ns or more b = 100 ns or more d = 400 ns or more do not read the white balance data and the af read data within the 1h period from the start of the v blanking. transfer specification pulse timing conditions type r2 ab d r2 270,000 pixels 410,000 pixels 100 ns 4.1 m s or more 70 ns 2.99 m s or more fs d {1 / fs (32 + 5) + 400 ns} or more sensor clock a = 100 ns or more b = 100 ns or more sld (pin 7) sdck (pin 6) transfer specification pulse timing conditions
HD49815TF 22 note: 2 to 9. function addresses the following table shows the function addresses for each function block (during state data transfer) and the data to be transferred from the microcomputer. table 2 function addresses for each function block and state data list of data transferred remarks 2 signal processing 3 tm write (setting example) (setting example) this example is related to sp-a0[9]. d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address stah stal std1 std2 this example is related to tm-a0 [14]. 00000000 ************************ 0000000000001001 d8 d7 d6 d5 d4 d3 d2 d1 ??????? d9 d8 d7 d6 d5 data read for automatic phase adjustment for sp1, sp2, and rg d4 d3 d2 d1 function address 00001001 w d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address 4 tm read stah stal std1 std2 00000001 ************************ 0000000100001110 d8 d7 d6 d5 d4 d3 d2 d1 ???????? d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address stah stal 00011000 ???? **** read area setting by stal (4 bits) d8 5 w 6 r d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address stah stal adata std1 std2 data 3 00000001 ********???***** 00000000 0000000110100010 ??? d5 d4 d3 d2 d1 00000000 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address stah adata stal std1 std2 00010 *********** ???? **** 00000000 00010100 ????? d3 d2 d1 ???????? 00000000 this example is related to the iris peak detection area. this example is related to the window h count 3. ae d8 d7 d6 d5 d4 d3 d2 d1 function address 00101000 white balance read hpf bandwidth selection base-clip quantity setting, etc. d8 7 w 8 r d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 window setting for white balance wb detection axis phase setting function address stah stal adata std1 0000000 *********???***** 0000000110110011 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address stah adata stal std1 std2 00100 ?????? ************* 00000000 00100 ?????? 00001 ?? d6 d5 d4 d3 d2 d1 00000000 this example is related to the offset r-b. this example is related to the v count 2. awb zoom note: for the zoom, the transfer of in total of seven bytes is required for the header and data 1 to 6. d8 d7 d6 d5 d4 d3 d2 d1 function address 00111 *** vf fetch address (read_cycle) d8 9 w 10 r d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 setting for integration and display gate function address stah stal adata std1 data 2 0000000111000 *********** 0000000111000101 d8 d7 d6 d5 d4 d3 d2 d1 data 1 d8 d7 d6 d5 d4 d3 d2 d1 d8 d7 d6 d5 d4 d3 d2 d1 function address stah adata stal 00110 *********** 00110000 ???? d4 d3 d2 d1 this example is related to the hrf bandwidth selection. this example is related to the differential gate of v-end. af d8 d7 d6 d5 d4 d3 d2 d1 header 10110 *** data 6 data 5 data 4
HD49815TF 23 digital interface timing the output specification and timing of the digital interface output (y, r-y, b-y) cpo (1 to 8) r-y2 r-y4 b-y4 b-y1 ypo (1 to 8) y2 y4 y5 y3 detailed specifications of digital interface timing : r-y/b-y determination pulse : clock dedicated to the digital interface (the clock generated from the external x'tal.) : digital interface output terminal : digital interface input terminal nryby dick cpo, ypo cpi, ypi cpo, ypo nryby dick dick output x'tal clk nryby (reference) r-y0 b-y0 y0 y1 4 : 2 : 2 output timing 35 nsec 70 nsec 2 to 15 nsec cpi, ypi 10 to 50 nsec 20 to 35 nsec
HD49815TF 24 package dimensions hitachi code jedec eiaj weight (reference value) tfp-120 conforms 0.5 g unit: mm *dimension including the plating thickness base material dimension 16.0 0.2 14 0.07 0.10 0.5 0.1 16.0 0.2 0.4 0.10 0.10 1.20 max *0.17 0.05 0 ?8 90 61 130 91 120 31 60 m *0.17 0.05 1.0 1.00 1.2 0.15 0.04 0.15 0.04
HD49815TF 25 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 1999. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra b e 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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